Locally-Routed Clock Tree Synthesis for FPGAs

Field Programmable Gate Arrays (FPGAs) are integrated circuits that can be programmed after manufacturing. It has applications in a wide variety of fields, from cryptography to machine learning. Computer Aided Design (CAD) tools are used to automate the process of programming FPGAs. Routing is a component of CAD that attempts to find an optimal design of wiring to connect logic blocks on an FPGA. Although it is an old problem, there are many interesting problems to solve and it is an active area of current research. An important problem in circuit design is the distribution of the clock signal to minimize the difference in signal arrival time (skew). In the Altera FPGA, the number of clock signals exceeds the available number of prefabricated wires dedicated for the clock. As a result, clock signals have to use wires meant to route data signals, and this must be incorporated into router design. I will be working on researching and developing novel algorithms in order to integrate clock signals into routing by reducing skew and improving quality of results.

Faculty Supervisor:

Paul Chow

Student:

Alvin Leung

Partner:

Intel

Discipline:

Computer science

Sector:

Advanced manufacturing

University:

University of Toronto