OIF 400-ZR Standard-Based DSP Architecture - ON-162

Preferred Disciplines: Electrical engineering, Mathematics (Masters, PhD or Post-Doc)
Company: Anonymous
Project Length: 1-2 years (16 units)
Desired start date: As soon as possible
Location: Ottawa, ON
No. of Positions: 4
Preferences: None

About the Company: 

Partner is an R&D company involved in the development of Intellectual Property for Networking and security (data communications telecommunications and Wireless).

Project Description:

The Project will develop an ultra low power and high gain preformance DSP for 400-ZR to be used in both Data Communciations and  Telecom Applications.

A new innovative DSP algorithm is needed to meet the stringent Power, Current and Real-Estate Requirments as set by the OIF 400ZR standard.  The target DSP design must be implemeneted in CMOS @ 7nm FinFET process. The trget market for  this DSP design is industry standard CFP and QSFP modules and sub-systems.

Therefore, interoperability is key as per OIF standard set requirements.

Research Objectives:

  • Thourough understanding of current/existing architecture of Cohernet DSP blocks.
  • Identify/Create new architectures using the a new or novel DSP algorithm to achieve the optimal power and highest performance acheiveable.
  • Select the most efficient architecture for FinFET process.
  • The algorithm must be verified using Matlab or C code for optimum power and performance.
  • The algorithm must be implementable in hardware (ASIC).
  • The algorithm must meet a predetermined power target for an (ASIC).

Methodology:

  • Identify target architectures to investigate new approches to meet DSP performance and power consumption.
  • Create C or C++ module for verification and modeling.
  • Create behavioral modeling in Verilog or VHDL for fast simulation.
  • Implement the module using Verilog or VHDL using synthesizable construct.
  • Create simulation environment to verify the design using SystemVerilog/C/etc.
  • Implement the design in FPGA and validate the algorithm in real FPGA. hardware
  • The design must meet the industrial standard for telecommunication.

Expertise and Skills Needed:

    • DSP knowledge for telecommunciations and Cohernet modem appliactions.
    • Knowledge of DSP archietecure.
    • DSP performance modeling.
    • Matlab/Octave modeling and simulation.
    • Logic design using Verilog or VHDL.

    For more info or to apply to this applied research position, please

    1. Check your eligibility and find more information about open projects
    2. Interested students need to get the approval from their supervisor and send their CV along with a link to their supervisor’s university webpage to Mel Chaar.
    Program: